Generally, shallow trench isolations (STIs) are used to separate and isolate active areas on a semiconductor wafer from each other. These STIs have historically been formed by etching trenches, overfilling the trenches with a dielectric such as an oxide, and then removing any excess oxide with a process such as chemical mechanical polishing (CMP) or etching in order to isolate the dielectric in the trenches. This dielectric helps to electrically isolate the active areas from each other.
However, by simply etching and filling the trenches, the corners of the trenches adjacent to the surface of the substrate are formed with a sharp, almost square shape. This sharp shape can cause significant cycling leakage, which detracts from the overall performance of the devices formed on the substrate. In an attempt to mitigate this cycling leakage, the corners of the substrate have historically been rounded by growing an oxide liner on the corner, thereby forming a rounded silicon corner.
However, this method of rounding the corners has only a limited efficiency. Further, as the scale of devices such as transistors is reduced to 45 nm below, the problems with cycling leakage will become more pronounced, and the oxide liner method of rounding the corners are not sufficient to handle the cycling leakage.
Accordingly, what is needed is a new method of rounding the corners of a substrate adjacent to an STI so as to minimize the cycling leakage for devices formed on the substrate.